The present invention generally relates to an apparatus and method for performing thin film layer thickness metrology and, in particular, to an apparatus for performing high resolution thin film layer thickness metrology including means for irradiating a surface of a layer of material with an array of focused monochromatic radiation.
One application wherein the present invention is especially practical, is in conjunction with measurements of silicon-on-insulator (SOI) semiconductor wafers. Typically, an SOI wafer consists of an Si/SiO.sub.2 /Si sandwich structure, and is fabricated by growing a silicon dioxide (SiO.sub.2) film on one surface of each of two silicon (Si) wafers and bonding the two silicon dioxide film surfaces together and annealing at high temperature. An outer surface of one of the two silicon wafers in the sandwich structure is then mechanically ground and polished to an average thickness of several microns. Unfortunately, this mechanical grinding and polishing results in large spatial variations in the thickness of this outer silicon layer. To reduce such spatial variations, a thickness error map indicating thickness non-uniformities in this outer silicon layer over its entire surface is required, for example, to initialize a micropolishing process.
One particular apparatus and method of obtaining such a thickness error map is described in U.S. patent application Ser. No. 07/804,872, filed on Dec. 6, 1991, entitled, Apparatus and Method for Measuring the Thickness of Thin Films, and assigned to the assignee hereof. The above-identified application is hereby incorporated herein by reference. Therein, thickness non-uniformities in the outer silicon layer are obtained by measuring reflectance characteristics over a full aperture of the outer silicon layer surface and then comparing this measured reflectance data to reference reflectance data by using numerical iteration or by using a calibration wafer having known outer silicon layer thicknesses. The reflectance characteristics are measured by projecting collimated monochromatic light onto the entire outer silicon layer surface such that coherent interactions occur in the light as it is reflected at the physical boundaries of the sandwich structure. As a result of these coherent interactions, an interference fringe pattern is formed on the outer silicon layer surface, a reflected image of which is captured by a charge coupled device (CCD) camera. From the captured interference fringe pattern image a reflectance map of the outer silicon layer is generated, the map is compared to reference reflectance data to determine the thickness non-uniformities in the outer silicon layer.
The above-described technique for obtaining thickness non-uniformities in the outer silicon layer is generally sufficient when thickness non-uniformities on the order of 200 .ANG./mm or greater must be detected. Such is the case since the imaging system used in that apparatus typically provides a lateral spatial resolution on the order of only 400 .mu.m, which is derived as follows.
Referring to FIG. 1, a schematic representation of the apparatus 1 used in the above-referenced patent application is shown. The resolution, d, is determined by the aperture, D, the focal length, f, of the imaging lens 64 in front of the CCD camera 30, and by the wavelength, .lambda., of the collimated monochromatic light 62 passing through the imaging lens 64. Typical values for these parameters are D.apprxeq.5 mm, f.apprxeq.1 m, and .lambda..apprxeq.900 nm, and their relation to the resolution, d, is given by the following formula, EQU d=2.44f.lambda./D
Applying the typical values to this formula, the corresponding typical value of the resolution is d.apprxeq.400 .mu.m.
Hence, the above-described apparatus and method of obtaining thickness non-uniformities in the outer silicon layer is generally not sufficient when thickness non-uniformities greater than 200 .ANG./mm are to be detected. The detection of such greater thickness non-uniformities is desirable not only with the outer silicon layer of the SOI wafer as described above, but also with semiconductor wafers in general whose outer layers have been lithographically patterned with integrated circuit designs. Such patterned wafers typically have thin film layer designs of circuit components that are smaller than 100 .mu.m in width with very large thickness non-uniformities (or gradients) along their edges. The detection of these thickness non-uniformities would allow precise verification that the thin film layer designs have been correctly patterned, in both location and thickness, into the semiconductor wafers. Consequently, extensive monitoring and control of integrated circuit fabrication processes could achieved. It is therefore be desirable to perform thin film layer thickness metrology with a higher lateral spatial resolution than is presently achieved with the prior art.